#42: Compiler processor tradeoffs for DISVLIW architectures


S.-H. Jee and K. Palaniappan

IEEE Int. Symp. On Parallel Architectures, Algorithms, and Networks (ISPAN), pgs. 175--180, 2002

parallelization, dod

PlainText, Bibtex, PDF, URL, DOI, Google Scholar

Abstract

The Dynamically Instruction Scheduled VLIW (DISVLIW) processor architecture is designed for balancing scheduling effort more evenly between the compiler and the processor. The DISVLIW instruction format is augmented to allow dependency bit vectors to be placed in the same VLIW word. Dependency bit vectors are added to each instruction format within long instructions to enable synchronization between prior and subsequent instructions. The DISVLIW processor dynamically schedules each instruction in long instructions using functional unit and dynamic scheduler pairs. Each dynamic scheduler dynamically checks for data dependencies and resource collisions while scheduling each instruction. Features such as explicit parallelism, balanced scheduling effort, and dynamic scheduling can be used to provide a sound frastructure for supercomputing. We simulate the DISVLIW architecture and show that the DISVLIW processor performs significantly better than the VLIW processor for a wide range of cache sizes and across numerical benchmark applications.