4 Publications by "S.-H. Jee"


#47: S.-H. Jee and K. Palaniappan

Performance of dynamically scheduling VLIW instructions

IEEE Int. Symp. System-on-Chip, pgs. 7--10, 2003

parallelization, dod

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#42: S.-H. Jee and K. Palaniappan

Compiler processor tradeoffs for DISVLIW architectures

IEEE Int. Symp. On Parallel Architectures, Algorithms, and Networks (ISPAN), pgs. 175--180, 2002

parallelization, dod

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#41: S.-H. Jee and K. Palaniappan

Performance analysis for a compressed-VLIW processor

ACM Symp. on Applied Computing, pgs. 913--917, 2002

parallelization, dod

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#39: S.-H. Jee and K. Palaniappan

Dynamically scheduling VLIW instructions with dependency information

8th IEEE Int. Symp. On High-Performance Computer Architecture and 6th Workshop on Interaction Between Compilers and Computer Architectures, pgs. 15--23, 2002

parallelization, dod

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