#46: Performance of dynamically scheduling VLIW instructions

S.-H. Jee and K. Palaniappan

IEEE Int. Symp. System-on-Chip, pgs. 7--10, 2003

parallelization, dod

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This paper evaluates performance of the dynamically instruction scheduled VLIW (DISVLIW) processor architecture. The DISVLIW processor architecture is designed for dynamically scheduling VLIW instructions using dependency information. Features such as explicit parallelism, balanced scheduling effort, and dynamic scheduling of VLIW instructions can be used to provide a sound structure for supercomputing. We simulate the DISVLIW processor architecture and show that the DISVLIW processor performs significantly better than the VLIW processor across various numerical benchmark applications.